The Fetch-Execute Cycle: The Full 7-Step Breakdown for IGCSE Computer Science (CIE)

The Fetch-Execute Cycle: The Full 7-Step Breakdown for IGCSE Computer Science (CIE)

What is the fetch-execute cycle?

The fetch-execute cycle is the repeating process a CPU uses to retrieve an instruction from main memory, decode what it means, and carry it out. It runs continuously while a computer is switched on, one instruction at a time, in seven distinct steps. Five registers, PC, MAR, MDR, CIR and ACC, and three system buses move data between the processor and memory at each stage.

For the exam, you need two things locked in: the order of the seven steps, and the exact register involved at each one. Get both solid and this stops being one of the scarier topics on the paper and turns into one of the more reliable sources of marks.

Quick checklist before you attempt a fetch-execute question

• Can you name all five registers (PC, MAR, MDR, CIR, ACC) and say what each one holds, without checking a table?

• Can you list the seven steps in order, not just describe the general idea in your own words?

• Do you know which bus carries an address versus which one carries the actual instruction or data?

• Can you say exactly when the PC increments, and why that timing matters?

• If the question says "explain" rather than "describe," do you know it wants a reason as well as a step?

What is Von Neumann architecture, and why does the CPU need it?

Almost every computer you've ever used runs on Von Neumann architecture: the design where program instructions and data live together in the same main memory, and the processor fetches both using the same set of buses. This is the Stored Program Concept. Instructions sit in memory exactly like data does, get moved to and from memory the same way, and get fetched, decoded and executed by the processor one after another.

Main memory itself is carved up into addressed locations, each one holding a fixed amount of binary content, each with its own unique address. Here's the part that trips people up: the CPU doesn't know what an instruction does until it's fetched it. It reads the binary pattern sitting at an address, then checks that pattern against the CPU's instruction set (the list of machine-code commands that specific processor can carry out) to work out what action it's actually being asked to perform.

What's actually inside the CPU, and what does each part do?

The CPU, also called the microprocessor or the processor, is built from five things: the ALU, the Control Unit, the system clock, a set of registers, and the buses connecting all of it to main memory. CIE examiners want you to state what each part does, precisely, not just recognise the acronym on a diagram.

The five main components

• Arithmetic and Logic Unit (ALU): carries out arithmetic operations (addition, subtraction, and so on) and logical or comparison operations (AND, OR, greater-than, equal-to).

• Control Unit (CU): coordinates the operations of memory, the processor, and input/output devices. Think of it as the conductor: it generates every signal that tells the rest of the CPU what to do and when.

• System clock: produces the regular timing signals, sent along the control bus, that keep every operation in the CPU synchronised. Without it, fetch and execute would have no shared timing to work against.

• Registers: tiny, extremely fast memory locations inside the CPU, each one holding a small amount of data or a single instruction at a time.

• Immediate Access Store (IAS): stores instructions the CPU has already fetched, ready to be used.

The three system buses

Three physical pathways move addresses, data and control signals between the CPU and main memory, and each one only carries one type of information. Mixing these up under exam pressure is one of the more common ways students lose a mark here, so it's worth knowing cold which bus is which and which direction each one travels.

Bus

Direction

What it carries

Address bus

Unidirectional (one-way, CPU to memory)

The memory address of the instruction or data location the CPU wants to access

Data bus

Bidirectional (both ways)

The actual data or instructions being transferred between the CPU and memory

Control bus

Bidirectional (both ways)

Control signals, such as read/write signals and the timing signals sent from the system clock

The five key registers

Five registers show up over and over in fetch-execute questions: the Program Counter, Memory Address Register, Memory Data Register, Current Instruction Register, and the Accumulator. Get this table properly memorised, not just recognised, because nearly every mark on this topic hinges on naming the right one at the right step.

Register

Full name

Function

PC

Program Counter

Holds the address of the next instruction to be fetched

MAR

Memory Address Register

Holds the address of an instruction or data; passes this address on to the MDR

MDR

Memory Data Register

Holds the data or instruction retrieved from the address in the MAR; passes it on to the CIR

CIR

Current Instruction Register

Holds the instruction currently being decoded and executed

ACC

Accumulator

Temporarily holds data during calculations carried out by the ALU

One way to keep these straight: the PC points at where you're going next. MAR and MDR are the delivery pair that actually fetch the instruction. CIR holds whatever's currently being worked on. ACC is just the CPU's scratchpad for arithmetic. Four registers, four jobs, don't blend them.

What are the seven steps of the fetch-execute cycle?

The fetch-execute cycle runs in seven steps. The PC holds the address of the next instruction, that address moves to the MAR, the instruction is fetched into the MDR, it moves from the MDR to the CIR, the PC increments by one, and the instruction is decoded and executed. CIE mark schemes reward the sequence itself, not just a list of the right registers in any order.

1. The Program Counter (PC) holds the address of the next instruction to be fetched.

2. That address is copied from the PC to the Memory Address Register (MAR), travelling along the address bus.

3. The instruction stored at that address in main memory (RAM) is fetched, travelling along the data bus.

4. The instruction is copied into the Memory Data Register (MDR), held there temporarily.

5. The instruction moves from the MDR into the Current Instruction Register (CIR).

6. The PC is incremented by 1, so it now points to the next instruction in the sequence.

7. The instruction in the CIR is decoded and executed.

Steps 1 to 6 are fetch. Step 7 is decode and execute, and CIE often splits that single step into two separate marking points. If a question asks you to "describe the fetch-decode-execute cycle" rather than just "the fetch-execute cycle," treat decoding and executing as two things worth writing down separately, not one.

What does one instruction actually look like moving through the fetch-execute cycle?

Say the CPU is about to run an instruction stored at memory address 200, and the PC currently holds the value 200. Here's exactly what happens, matching the seven steps above.

1. PC holds the next address. The PC contains 200, the address of the instruction due to run next.

2. Address copied to MAR. 200 moves from the PC into the MAR via the address bus. The MAR now effectively says: fetch whatever is stored at 200.

3. Instruction fetched from memory. Main memory looks up address 200 and sends back the binary instruction stored there, travelling along the data bus.

4. Instruction copied into MDR. That binary instruction sits in the MDR temporarily.

5. Instruction moves to CIR. The instruction moves from the MDR into the CIR, ready to be worked on.

6. PC incremented. The PC changes from 200 to 201, now pointing at the next instruction in the sequence. This happens no matter what the current instruction turns out to do.

7. Decode and execute. The Control Unit decodes the binary pattern in the CIR against the CPU's instruction set and works out what it means, say, "add the value in this memory location to the ACC." The ALU performs the addition. The result lands in the Accumulator (ACC).

The cycle repeats immediately, starting again with whatever address is now sitting in the PC. That's 201.

Why does the PC increment before the instruction has even finished executing?

Because the CPU needs to already know where to fetch from next, regardless of what the current instruction turns out to do. Incrementing at step 6, before execution happens at step 7, keeps fetching and executing decoupled from each other.

That decoupling matters most with jump or branch instructions. If executing the current instruction changes the PC directly, that new value simply overwrites the incremented one before the next fetch starts. So if you're asked why the increment happens where it does, "decoupling" is closer to the mark scheme's actual answer than "because it needs to move to the next instruction," even though both sound like they're saying the same thing.

What mistakes actually cost marks on fetch-execute questions?

Four mistakes account for most of the marks lost on this topic, and none of them are about misunderstanding the concept.

• Swapping MAR and MDR. MAR holds an address, where to look. MDR holds the actual data or instruction found there, what was found. Students who reverse these usually still describe the right process; they just name the wrong register at the wrong step.

• Treating the PC increment as part of "fetching the instruction" instead of its own step. It's step 6, on its own, not folded into step 3.

• Writing "execute" as one action when the question wants "decode" and "execute" separately. This mostly costs marks on "describe the fetch-decode-execute cycle" questions specifically.

• Getting a bus direction wrong, for instance saying the address bus carries data, or forgetting that the address bus only travels one way.

Every one of these is fixable by drilling the sequence out loud, register by register, until naming them is automatic, not by re-reading the explanation one more time.

You already understand it.

What's missing is retrieval under pressure, not comprehension.

If you want to drill this until it's automatic under timed conditions, the Question Bank has topic-filtered past paper questions on exactly this, rather than general CPU architecture questions with one fetch-execute question buried somewhere in them.

How do CIE exam questions actually phrase this?

CIE fetch-execute questions tend to lean on one of four command words, and each one wants something slightly different from you.

• "Name" or "state" wants the register or component itself, nothing more. "State which register holds the address of the next instruction" wants one word: PC.

• "Describe" wants the steps or the process, in the right order, without necessarily justifying why any of it happens.

• "Explain" wants a reason attached, not just a step. "Explain why the PC is incremented during the fetch stage" needs the decoupling reasoning from the section above, not just "so it points to the next instruction."

• "Compare" or "distinguish between" shows up most often for MAR versus MDR, and wants the difference stated directly: one holds an address, the other holds what was found at that address.

Get the command word wrong and you can write a technically accurate paragraph that still scores zero, because you've answered a different question than the one that was asked.

How should you actually revise this before the exam?

Don't revise this by re-reading the seven steps until they look familiar. Familiar isn't the same as recallable under exam conditions. Instead: cover the register table, say all five from memory, then check. Do the same with the seven steps, in order, without looking. Then trace a made-up instruction through the whole cycle yourself, the way the worked example above does, using a different starting address.

If you want a quick way to check whether your own written explanation would actually get the marks, rather than just sounding right to you, the AI Tutor can grade a written answer against what a CIE mark scheme is actually looking for, register by register, instead of just telling you the general idea was right.

FAQ

Is the fetch-execute cycle the same as the fetch-decode-execute cycle? Yes, they're the same process described two ways. Some sources treat step 7 as one action, "execute." Others split it into "decode" then "execute," for eight described actions instead of seven. CIE tends to mark decoding and executing as separate points, so mention both explicitly when a question uses the longer name.

What's the difference between the MAR and the MDR? The MAR holds an address: where to find something in memory. The MDR holds the actual data or instruction found at that address. MAR asks where. MDR receives what.

Does the fetch-execute cycle use the accumulator every time? No. The ACC only comes into play when an instruction involves a calculation through the ALU, an addition, for example. Fetching, decoding, and some execute steps, like a jump, never touch the ACC at all.

Why is it called Von Neumann architecture? It's named after John von Neumann, who described the stored-program concept in 1945: storing instructions and data together in the same main memory, addressed and accessed the same way, rather than keeping instructions on separate hardware.

What's the single most common mark lost on fetch-execute questions? Naming the wrong register at a given step, most often swapping MAR and MDR, or treating the PC increment as part of "fetching the instruction" rather than its own separate step. Both are memorisation slips, not gaps in understanding, which is exactly why they're worth fixing well before results depend on it.